module mux16_4to1 #(parameter DATA_WIDTH = 16,
                    parameter SEL_WIDTH = 4)
                   (input [DATA_WIDTH-1:0] D_IN0,
                    D_IN1,
                    D_IN2,
                    D_IN3,
                    input [$clog2(SEL_WIDTH)-1:0]SEL, output reg [DATA_WIDTH-1:0] D_OUT);
    always @(D_IN0,D_IN1,D_IN2,D_IN3,SEL) begin
        case(SEL)
            2'b00:D_OUT <= D_IN0;
            2'b01:D_OUT <= D_IN1;
            2'b10:D_OUT <= D_IN2;
            2'b11:D_OUT <= D_IN3;
        endcase
    end
endmodule
